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Principal Design Engineer

Cadence

  • Pune
  • Posted 8 months ago
  • Full-time
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About this role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.

  • 7+ years of Design Verification experience with SV/UVM

  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.

  • Design Verification experience verifying complex designs and leading projects from concept to verification closure.

  • Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.

Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.

We’re doing work that matters. Help us solve what others can’t.

Jobs Hindustan copied this listing from Cadence's official careers site on 30 October 2026 and checked it again 31 October at 6:04 am IST. Cadence never asks candidates for money. If anyone does, it is a scam.

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